Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

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Hence this is also called as Swap gate. In the reversible logic circuit design, fan-out and feedback are not permitted [4]. Complement reversible multiplier cell Wkoley. The conclusion of the above discussion is that, it is evident that the proposed reversible Baugh-Wooley multiplier circuit design is better than the existing designs with respect to gate counts, garbage inputs and garbage outputs. The proposed reversible Baugh-Wooley multiplier circuit is more efficient compared to the existing circuits presented by [5] [7] – [9].

The Toffoli gate synthesis of the proposed wopley multiplier cell is also given.

Function wise Peres Gate will be equal with the bit conversion generated by a Toffoli Gate succeeded by a Feynman Gate. Computer arithmetic – algorithms and hardware designs Behrooz Parhami Let the numbers to be multiplied be A and B. This can be understood easily with the help of the comparison results shown in Table 1. The work [7] also follows the same strategy as the previous two works, multiplication in two steps. The functions S and T will produce sum and carry outputs respectively of the complement function of the Baugh- Wooley structure.


Even the proposed design is having moderate garbage outputs; we can conclude that this design is better in terms of number of gates and constant inputs. In [6]the authors have proposed a new reversible gate called as HNG gate.

The proposed reversible multiplier cells are capable of multiplying 2 bits in the current array and add the result with the sum and carry outputs of previous array. Dooley is in section 6. The proposed reversible Baugh- Wooley multiplier design produces 48 wloley outputs, but the design in [5] [7] – [9] produces 52, 52, 40 and 49 garbage outputs respectively.

International Journal on Engineering Science and Technology, 2, In the recent years various reversible multiplier designs multippier been proposed [5] – [9]. Section 2 is an overview of basic reversible gates. Therefore, it is clear that this is the better design than the existing counterparts.

Therefore the proposed multiplier cells are evaluated based on the Gate count, Garbage inputs and Garbage outputs.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog – Semantic Scholar

The multiplier A and the multiplicand B can be represented as. A circuit will be known as reversible if it can bring back the inputs from haugh outputs. The input A is the multiplier bit. Topics Discussed in This Paper. Data-dependent truncation scheme for parallel multipliers Multlplier KingE.

The results and discussions of the proposed reversible Baugh-Wooley multiplier are presented in section 5. This gate is also known as Controlled-Not gate. These reversible multiplier cells are targeted for reversible Baugh-Wooley multiplier design.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

Therefore, the hardware intricacy of the proposed design is less compared to the existing approaches. In [8]the authors have proposed a new reversible gate called as RAM gate. It has been done in two steps as follows: Circuits and Systems07From This Paper Figures, tables, and topics from this paper. Information Technology Journal, 8, Besides, synthesizing reversible logic circuits is much difficult than conventional irreversible logic circuits due to the constraints.


Tab stop Adder electronics Field-programmable gate array Multiplication. This gate is mainly used as a copying gate as fan-out is not allowed in reversible logic design.

Out of the five outputs, two outputs Q and R are left unspecified, since these are the garbage outputs. Reversible multiplier cell MC.

The input D is the sum input from the previous cells. This constraint forces the number of inputs to be equal to the number of outputs [3] [4]. The organization of the paper is as follows.

In the block diagram shown in Figure 5three types of cells are used. A detailed representation and explanation is done in this multipoier. International Journal of Theoretical Physics, 21, The final product could be generated by subtracting the last two positive terms from the first two terms. Feynman Gate FG can be used as a copying gate.

The input B is the multiplicand bit. References Publications referenced by this paper. Optical News, 11, This work also involves two steps as in [5].